1. Field of the Invention
The present invention relates to computer systems, and, more particularly, to clock generation and debugging techniques.
2. Description of the Related Art
Computer systems are information handling systems which can be designed to give independent computing power to single or multiple users. Computer systems have attained widespread use and may be found in many forms including mainframes, minicomputers, workstations, file servers, embedded systems and personal computer systems. Computer systems, such as the International Business Machines (IBM) compatible personal computer system, typically include a processor, memory, and various input/output (I/O) devices. A personal computer system is usually distinguishable by the use of a system board to electrically connect these components together. Computer systems may include more than one processor chip. For example, a personal computer system board may include two processors, one for general control and integer calculations and one for floating point or multimedia applications.
Computer systems operate according to various system clocks. Typically, an external clock is supplied to a processor which uses the external clock to generate a processor clock. If the external clock frequency is equal to the processor clock frequency, each clock is referred to as a 1X clock. Alternatively, the external clock may be modified internally by the processor so that the clocks have different frequencies. For example, a processor may double the frequency of the external clock to generate a 2X processor clock. Because the internal processor clock operates at twice the frequency of the supplied external clock, the external clock can be lower than would otherwise be necessary. The external clock is typically doubled by the processor to avoid electromagnetic emission problems that occur at higher external clock frequencies (e.g., 100 MHz or more) and to avoid high frequency difficulties that can occur at the pads of a processor.
Computer systems are often debugged using debug testers. An exemplary debug tester is the J971 brand debug tester available from Teradyne. Debug testers such as the J971 often input an array of predetermined information to the processor. Each line of the input array typically corresponds to the input signals during one clock cycle. The debug tester clocks the processor while inputting successive lines of the input array. The debug tester receives an array of output information from the processor. The received output array is then compared to an array of expected output information to check for errors.
Debug testers are often used to test time-critical paths or "speed paths." Speed paths exist where the combinational delay through a path of a circuit is greater than the time allocated for that path. Thus, latches at the end of a speed path close without a valid input, possibly resulting in incorrect data being driven to the processor outputs. For example, if a debug tester determines that a line of the received output array is not the same as the corresponding line of the expected output array, a speed path may exist. However, the speed path that caused the output error could have caused the error many clock cycles prior to the clock cycle of the unexpected output. Accordingly, the cycle in which the speed path occurred must be determined.
When a speed path failure occurs during debug analysis, stretch or slowdown cycles may be used to isolate the internal device failing cycle. A stretch cycle extends the period of a clock in a particular cycle when a speed path could exist. The extra time resulting from the increased clock period usually allows sufficient propagation time to produce valid circuit outputs. For example, if a particular path has an 11.5 ns propagation time, and the clock period is 10 ns, the particular path is a speed path. By stretching the clock period to, e.g., 20 ns, sufficient time is given for the signal to propagate through the path.
Upon discovering a speed path error in the output array, the debug tester reapplies the input array to the processor inputs a number of times. A different clock cycle is stretched during each application of the input array until a pass condition (expected data equals received data) exists for the line of the array in which the initial discrepancy occurred. By stretching the clock period of the first clock cycle during a first test run, and then stretching the clock periods of subsequent clock cycles during subsequent test runs, the clock cycle in which the speed path occurred is discovered. Since the stretching of the clock period permitted the signal to propagate through the speed path, the stretched cycle of the test run in which valid outputs are obtained indicates in which cycle the speed path occurred.
For example, if an error occurred in line 50 of the output array (i.e., cycle 50), the speed path may have occurred in any of cycles 1-49. Therefore, the debug tester applies the input array and stretches clock cycle 1. Next, the debug tester applies the input array and stretches clock cycle 2, and so on. If, e.g., a pass condition exists for line 50 in test run 45, then the clock cycle that was stretched in test run 45 (e.g., cycle 45) is the clock cycle in which the speed path error occurred that caused the discrepancy in line 50.
Stretch cycles in the 1X static clock may be used to isolate the internal device failing cycle. Changing the period of a single phase is straightforward when using a 1X static clock since the external clock is used to directly produce the internal clock phases. Thus, the stretch cycles can be provided by the external clock.
As system clock frequencies increase, the use of debug testers to test computer systems becomes increasingly problematic. For example, debug testers that test speed paths can typically test computer systems having a system clock frequency within a predetermined frequency range. When a processor exceeds the debug tester's maximum frequency, a new debug tester must be acquired in order to test speed paths on the higher frequency processor.